This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-246575, filed Aug. 31, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to the formation of an element-isolating area and a gate electrode, and more particularly to a semiconductor device used as a memory cell, and its manufacturing process.
FIG. 31 shows an example of a conventional SRAM memory cell array. This figure only shows element-isolating areas 64a, element areas 64b, gate electrodes 66a and local interconnection layers 70a. A process for manufacturing a unit memory cell section 59 will be described.
First, as shown in FIG. 32, an insulating film 61 is formed on a semiconductor substrate 60, and a nitride film 62, for example, which is used as a stopper during polishing a filling material, is formed on the insulating film 61.
Subsequently, as shown in FIG. 33, a patterned resist 63 is formed on the nitride film 62. Using the resist 63 as a mask, the nitride film 62, the insulating film 61 and the semiconductor substrate 60 are selectively etched by anisotropic etching, thereby forming an element-isolating trench 64. The etching of the semiconductor substrate 60 is not limited to that using the resist 63 as a mask. For example, the pattern of the resist 63 may be copied on the nitride film 62, thereby etching the semiconductor substrate 60 using the nitride film 62 as a mask. Then, the resist 63 is removed and oxidation is executed.
After that, as shown in FIG. 34, an oxide film 65, for example, is formed on the entire surface of the resultant structure, thereby filling the element-isolating trench 64 with the oxide film 65.
Then, as shown in FIG. 35, the oxide film 65 is etched by dry etching or CMP (Chemical Mechanical Polishing), so as to expose the top surface of the nitride film 62.
Thereafter, as shown in FIG. 36, the nitride film 62 and the oxide film 65 are removed to form the element-isolating area 64a. Then, ion implantation is executed for forming a well or a channel, and the insulating film 61 is removed.
As shown in FIG. 37, a gate insulating film 61a is newly formed on the semiconductor substrate 60. A polysilicon film 66, which will be formed into gate electrodes, is formed on the gate insulating film 61a. On the polysilicon film 66, a patterned resist 67 is formed.
Subsequently, the polysilicon film 66 is etched using the resist 67 as a mask. As a result, gate electrodes 66a are formed as shown in FIG. 38, followed by the removal of the resist 67.
As is shown in FIG. 39, an interlayer insulating film 68 is formed on the entire surface of the resultant structure, and a pattern resist (not shown) is formed on the interlayer insulating film 68. The interlayer insulating film 68 is etched, using the resist as a mask, thereby providing local interconnection layer forming sections 69. After that, a metal film 70 is formed on the entire surface, thereby filling the interconnection layer forming sections 69. The metal film 70 is then etched to expose the top surface of the interlayer insulating film 68. Thus, the local interconnection layers 70a are formed. FIG. 40 is a plane view of the structure shown in FIG. 39. Further, FIG. 41 is a cross sectional view taken along line 41xe2x80x9441 of FIG. 40.
In the above-described conventional technique, the patterned resist 67 is formed as shown in FIG. 37 when forming the gate electrodes 66a for MOS transistors. FIG. 42 is a plane view of the structure shown in FIG. 37.
As is shown in FIG. 42, the resist 67 is formed on an inverter section 65a and a transfer section 65b. At this time, it is necessary to pattern the resist 67 in consideration of any possible misalignment from an underlayer pattern (e.g. the element areas 64b) of lithography process. Accordingly, a so-called fringe F1 serving as an allowance for misalignment is provided, resist 67 is designed rectangle of pattern length L1.
However, where the resist 67 to be exposed must be made to have a small size in accordance with the development of the element refining technique, the resist 67 cannot be patterned as desired. For example, as is shown in FIGS. 42 and 43, even if the resist 67 is tried to be formed into the rectangle of pattern length L1, a resist pattern 67a with a length of as short as L2 is formed. When such a shortening phenomenon occurs, the fringe becomes shorter from F1 to F2, and it is possible that the resist pattern 67a will be smaller than a required minimum pattern which includes an allowance for misalignment. In this case, normal transistor operation cannot be executed.
To solve the above problem, there is a process for elongating the length F1 of the fringe by the amount of shortening when patterning the resist 67. However, if the fringe is elongated, the entire cell inevitably enlarges. Accordingly, when realizing a memory cell array of a large capacity, the chip size inevitably enlarges.
A process for reducing a gate electrode space S1 could be used as a process for increasing the length F1 of the fringe without increasing the cell size. However, if the resolution limit is exceeded as a result of reducing S1, electrodes to be isolated from each other (for example, an electrode 66a in the inverter section 65a and a electrode 66a in the transfer section 65b shown in FIG. 40) will be connected. This also disables the normal transistor operation.
As described above, the conventional gate electrode forming process and memory cell structure makes it very difficult to realize a minute memory cell of a large capacity.
The present invention has been developed to solve the above-described problem, and aims to provide a semiconductor device, which includes a minute memory cell of a large capacity, and is free from a gate fringe or shortening phenomenon problem, and also can provide a process for manufacturing the semiconductor device.
To attain the aim, the present invention uses the following means.
The semiconductor device of the invention comprises element areas formed in a semiconductor substrate; an element-isolating area that isolates the element areas from each other; and a plurality of gate electrodes formed only on each of the element areas.
Further, the semiconductor device of the invention comprises element areas formed in a semiconductor substrate; an element-isolating area that isolates the element areas from each other; and a plurality of gate electrodes formed only on each of the element areas; a first local wire connecting the gate electrodes to each other; and a second local wire connecting the element areas to each other.
Furthermore, the semiconductor device of the invention comprises element areas formed in a semiconductor substrate; an element-isolating area that isolates the element areas from each other; and a plurality of gate electrodes formed only on each of the element areas; a first local wire connecting the gate electrodes to each other; a second local wire connecting the element areas to each other; a plurality of third local wires that are each formed only on a corresponding one of the element areas and do not connect the gate electrodes or the element areas; and a wire connecting the third local wires.
Also, the semiconductor device of the invention comprises element areas formed in a semiconductor substrate; an element-isolating area that isolates the element areas from each other; a plurality of gate electrodes formed only on the element areas; a first local wire connecting the gate electrodes to each other; a plurality of second local wires each formed on a corresponding one of the element areas, the second local wires connecting no gate electrode or no element areas; and a wire connecting the second local wires.
The semiconductor device of the invention may further comprise side walls formed on side surfaces of the gate electrodes.
Preferably, the semiconductor device of the invention further comprises low density diffusion areas formed in those surface portions of each of the element areas, which are overlap respective lower edge portions of the gate electrodes, and high density diffusion areas having a higher impurity concentration than the low density diffusion areas and formed in surface portions of the element areas in contact with the low density diffusion areas.
More preferably, the semiconductor device of the invention further comprises a silicide film formed on the gate electrodes and the element areas.
It is desirable that the element-isolating area should have a trench structure.
Also preferably, the gate electrodes is formed of a material different from the material of the first and second local wires.
Preferably, the second local wire is thicker than the gate electrodes.
The present invention also provides a process of manufacturing a semiconductor device comprising the steps of: forming a gate insulating film on a semiconductor substrate; forming a gate electrode material on the gate insulating film; forming an element-isolating area in the semiconductor substrate for isolating element areas from each other; forming a patterned resist on the gate electrode material; selectively removing the gate electrode material, using the resist as a mask, thereby forming a plurality of gate electrodes only on those portions of the gate insulating film, which are located on the element areas; removing the resist; forming an interlayer film on an entire surface of a resultant structure; and forming local wires in the interlayer film for connecting the gate electrodes to each other and the element areas to each other.
The present invention provides a process of manufacturing a semiconductor device comprising the steps of: forming a gate insulating film on a semiconductor substrate; forming a dummy gate material on the gate insulating film; forming an element-isolating area in the semiconductor substrate for isolating element areas from each other; forming a patterned resist on the dummy gate material; selectively removing the dummy gate material, using the resist as a mask, thereby forming a plurality of dummy gates only on those portions of the gate insulating film, which are located on the element areas; removing the resist; forming a first interlayer film on an entire surface of a resultant structure; flattening the first interlayer film to expose top surfaces of the dummy gates; removing the dummy gates to form openings; implanting ions through the openings; forming a gate electrode material on an entire surface of a resultant structure and filling the openings; selectively removing the gate electrode material to expose a top surface of the first interlayer film and form gate electrodes in the openings; forming a second interlayer film on an entire surface of a resultant structure; and forming local wires in the second interlayer film for connecting the gate electrodes to each other and the element areas to each other.
Preferably, the process of the invention further comprises the step of forming side walls on side surfaces of the gate electrodes.
Preferably, the process of the invention further comprises the steps of: forming low density diffusion areas in those surface portions of each of the element areas, which are overlap respective lower edge portions of the gate electrodes; and forming high density diffusion areas, which have a higher impurity concentration than the low density diffusion areas, in surface portions of the element areas in contact with the low density diffusion areas.
More preferably, the process of the invention 11, further comprises the step of forming a silicide film on the gate electrodes and the element areas.
Also preferably, the process of the invention further comprises the steps of: removing, after ion implantation, the gate insulating film from a bottom of each of the openings to expose top surface portions of the semiconductor substrate; and forming again an insulating film on the exposed surface portions of the semiconductor substrate.
As described above, the present invention can provide a semiconductor device, which includes a minute memory cell of a large capacity and is free from a gate fringe or shortening phenomenon problem, and also can provide a process for manufacturing the semiconductor device.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.